/* Stvrtok 22.9.2022 8,00-10,30(2.5h) a 13,00-19,00(6h)  STUDY Resers k teme „Tvorba modelov SiC MOSFET tranzistorov v SPICE“

 STUDIUM:
— Resers k teme tvorbe a pouzitie modelov SiC MOSFET tranzistorov v SPICE
— preskumana cast odkazov vytvorena Googlom na zaklade vyhladavcich slov : „sic mosfet pspice model“

ULOHY PRE DIPLOMANTA DP VLCEK :
 1. Do ktorej kapitoly DP by sa mala zaradit tato tema ?

 2. ZAKLADNA ULOHA: Prejst si uvedene zdroje informacii s cielmi:  
  — porozumiet ako sa buduje staticky (zakladny) model SiC MOSFET tranzistoru a dalsie urovne SPICE modelu zahrnujuce uz vplyv teploty
— osvojit si rozne varianty (levely) SPICE modelov SiC MOSFET tranzistorov/vykonovych modulov (firmy Infineon, Wolfspeed, MICROCHIP ….)
— osvojit si pracu s externymi modelmi SiC MOSFET (Wolfspeed, Infineon, ROHM) ci uz v LTSpice (tento program sa musi pouzit v diplomovej praci),  ale aj v inych programoch (Infinieon Designer, Speedfit od Wolfspeed)
— premysliet si ako by som modeloval v programe LTspice vybijanie DC link kapacit s dvoma SiC MOSFET tranzistormi od WolfSpeed a potom od Infinieonu (jeden tranzistor ON a druhy v linearnom rezime aktivnej zataze) – cielom je priblizit sa simulaciami k datasheetu tranzistoru
— ako by som zohladnil pri tychto simulaciach narast teploty puzdier SiC MOSFET tranzisorov pocas procesu vybijania
— porozumiet z datasheetu budica (Evakit FRDMGD3162HBIEVM ) ako sa pouzity budic adaptuje na rezim aktivneho vybijania DC link kapacitorov – ako sa lisia budice s a bez moznosti aktivneho vybijania  
 
3. Ciastkove ulohy :  
 — ad [2] Zohnat IEEE clanok („A Physically Based Scalable SPICE Model for Silicon carbide Power MOSFETS, Canhong He, James Victory, APEC 2017, link: https://www.semanticscholar.org/paper/A-physically-based-scalable-SPICE-model-for-silicon-He-Victory/ee71758e30c727f5ef71dfaa44b11d775ebe449f „)
 — ad [3] Vytypovat SiC MOSFET Modul/tranzistor najblizssi pouzitemu v DP (vybrat to podla datasheetu)a vyziadat ho cez stranku   https://www.infineon.com/models
 — preskumat na tejto stranke ponuky roznych modelov – medzi nimi su modely SPICE a PSPICE
 — ad [10][20]- zohnat tieto IEEE clanky
 — Zaradit info o programe PLECS  [26] do diplomovej prace, odskusat si tento program

— POZNAMKA :

• Subory oznacene ako LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\ su aj na Google Drive kde maju DP VLCEK a DP BLASKO pristup do adresara  LINK

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SUMARIZACIA ESERSE  PODLA TEM :
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Suhrnne informacie:
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— [13] (2020) aktualny status vyvoja PEU v SG vratane uvedenia potencionalnych dodavatelov SIC
— [14] (2020)Schaeffler material (2020): E-Motor & PEU

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Firemne informacie vyrobcov o komponentoch SiC MOSFET/VYKONOVE MODULY
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— [3] TOP INFO: rozne informacie o SiC vykonovych suciastkach a modeloch roznych typov SiC vykonovych prvkov spolocnosti Infinieon (dolezite je napr. zavedenie tepelne zavislych modelov)
— [25] Firemne materialy (2020): WolfSpeed – potencialny dodavatel pre SG, modely nimi vyrabanych tranzistorov SiC MOSFET, priklady simulacie obvodov v programoch LTSpice a PSIM, ako v elektronickej simulacii zohladnit vplyv meniacej sa teploty teploty puzdra
— [26] Informacia o simulacnom programe PLECS (2022) spolocnosti PLEXSIM – program je urceny pre vykonovu elektroniku, ma STANDALONE verziu a verziu ako blockset pre SIMULINK, spomina ho Wolfspeed
— [11] TOP zdroj pre diploma thesiss s vybornou literaturou : Firemny material ONSEMI (2021 – NOVY!)Physically Based, Scalable SPICE Modeling Methodologies for Modern Power Electronic Devices najkompaktnejsi popis zakladneho modelu SiC MOSFET a SiC IGBT vratane popisu verifikacie tohoto modelu
— [12] TOP zdroj pre diploma thesiss: ROHM webstranky o SiC vykonovych polovodicoch vratane vyborneho PDF materialu – podla [13] jeden z potencialnych dodavatelov SiC komponentov pre SG
— [24] Firemny material (2020): MICROCHIPpopis modelov SiC vykonovych komponenetov

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Ako vytvorit SPICE model SiC MOSFET tranzistora
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— [1] ako vyzera vytvorenie SPICE modelu pre SiC MOSFET – odkaz na zdrojovu IEEE publikaciu
— [4] podrobny popis vytvorenia modelu SiC MOSFET tranzistora a tiez popis ako sa model overi
— [5] klucovy clanok navod ako vytvorit SPICE model z udajov v datasheete
— [7] dalsi clanok o modeli SiC MOSFET tranzistora
— [8] dalsi clanok o modeli SiC MOSFET tranzistora
— [20] Clanok IEEE (2017): Analysis of SPICE models for SiC MOSFET power devices
— [22] Clanok(2022): Specifika modelovania SiC MOSFET
— [23] Clanok (2016): PSpice Modeling Platform for SiC Power MOSFET Modules with Extensive Experimental Validation

TEPELNE ZAVISLY MODEL SPICE:
— [15] Clanok : Temperature Dependent Pspice Model of Silicon Carbide Power MOSFET
— [18] clanok (2017): modelovanie SiC MOSFET so zapocitanim tepelnych procesov

MATLAB:
— [10] Clanok (2015), zamknuty IEEE clanok , abstrakt hovori o simulacii v MATLAB-e a validacii tohoto modelu
— [19] vedecky clanok (2021): prostredie MATLAB

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Ako pouzivat hotove modely SPICE SiC MOSFET tranzistora:
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— [2] simulacny SW LTSpice a ako pracovat s uz hotovym modelom SiC MOSFET vytvorenym firmou Wolfspeed (podla [13] jeden z potencialnych dodavatelov SiC komponentov pre SG
— [6] velmi popisny clanok od Cadence (vyraba OrCAD)o modeloch SiC MOSFET- povazujem ho za klucovy pohlad experta na modely SiC MOSFET
— [9] Informativny clanok(2012) Wolfspedd (byvaly Cree) je firma vyrabajuca SiC MOSFET-y, clanok informuje o vlastnych tepelne zavislych modeloch SPICE a o tom ako ich zaintegrovat do LTSpice-suvis s videom [2]
— [16] TOP INFO Technical Article (2020): How to Simulate Silicon Carbide Transistors with LTspice
— [17] technical Articel (2020): tazisko simulacie v LT Spice je tu kladene na budenie driverom
— [21] technicky clanok (2020): modelovanie SiC MOSFET v LTSpice, prakticke skusenosti

SUMAR STUDIA :
— [1] ako vyzera vytvorenie SPICE modelu pre SiC MOSFET – odkaz na zdrojovu IEEE publikaciu
— [2] simulacny SW LTSpice a  ako pracovat s uz hotovym modelom SiC MOSFET vytvorenym firmou Wolfspeed (podla [13] jeden z potencialnych dodavatelov SiC komponentov pre SG)
— [3] TOP INFO: rozne informacie o SiC vykonovych suciastkach a modeloch roznych typov SiC vykonovych prvkov spolocnosti Infinieon (dolezite je napr. zavedenie tepelne zavislych modelov)
— [4] podrobny popis vytvorenia modelu SiC MOSFET tranzistora a tiez popis ako sa model overi
— [5] klucovy clanok navod ako vytvorit SPICE model z udajov v datasheete
— [6] velmi popisny clanok od Cadence (vyraba OrCAD)o modeloch SiC MOSFET- povazujem ho za klucovy pohlad experta na modely SiC MOSFET
— [7] dalsi clanok o modeli SiC MOSFET tranzistora
— [8] dalsi clanok o modeli SiC MOSFET tranzistora
— [9] Informativny clanok(2012) Wolfspedd (byvaly Cree) je firma vyrabajuca SiC MOSFET-y, clanok informuje o vlastnych tepelne zavislych modeloch SPICE a o tom ako ich zaintegrovat do  LTSpice-suvis s videom [2]
— [10] Clanok (2015),  zamknuty IEEE clanok , abstrakt hovori o simulacii v MATLAB-e a validacii tohoto modelu
— [11] TOP zdroj pre diploma thesiss s vybornou literaturou :  Firemny material ONSEMI (2021 – NOVY!)Physically Based, Scalable SPICE Modeling Methodologies for Modern Power Electronic Devices najkompaktnejsi popis zakladneho modelu SiC MOSFET a SiC IGBT vratane popisu verifikacie tohoto modelu
— [12] TOP zdroj pre diploma thesiss: ROHM webstranky o SiC vykonovych polovodicoch vratane vyborneho PDF materialu – podla [13] jeden z potencialnych dodavatelov SiC komponentov pre SG
— [13] (2020) aktualny status vyvoja PEU v SG vratane uvedenia potencionalnych dodavatelov SIC
— [14] (2020)Schaeffler material (2020): E-Motor & PEU
— [15] Clanok : Temperature Dependent Pspice Model of Silicon Carbide Power MOSFET
— [16] TOP INFO Technical Article (2020): How to Simulate Silicon Carbide Transistors with LTspice
— [17] technical Articel (2020): tazisko simulqcie v LT Spice  je tu kladene na budenie driverom
— [18] clanok (2017): modelovanie SiC MOSFET so zapocitanim tepelnych procesov
— [19] vedecky clanok  (2021): prostredie MATLAB
— [20] Clanok IEEE (2017): Analysis of SPICE models for SiC MOSFET power devices
— [21] technicky clanok (2020): modelovanie SiC MOSFET v LTSpice, prakticke skusenosti
— [22] Clanok(2022): Specifika modelovania SiC MOSFET
— [23] Clanok (2016): PSpice Modeling Platform for SiC Power MOSFET Modules with Extensive Experimental Validation
— [24] Firemny material (2020): MICROCHIPpopis modelov SiC vykonovych komponenetov
— [25] Firemne materialy (2020): WolfSpeed – potencialny dodavatel pre SG, modely nimi vyrabanych tranzistorov SiC MOSFET, priklady simulacie obvodov v programoch LTSpice a PSIM, ako v elektronickej simulacii zohladnit vplyv meniacej sa teploty teploty puzdra
— [26] Informacia o simulacnom programe PLECS (2022) spolocnosti PLEXSIM  – program je urceny pre vykonovu elektroniku, ma STANDALONE verziu a verziu ako blockset pre SIMULINK, spomina ho  Wolfspeed

ZDROJE A POPIS CO V NICH JE :
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[1] ON SEMICONDUCTOR SiC MOSFET Corner and Statistical SPICE Model Generation
— [1] clanok sa venuje statistickym modelom vykonovych tranzistorov postavenych na SPICE postavenom na fyzikalnom modeli SiC MOSFET
— slajd 5. „Physically Based SPICE Models“ ukazuje ako vyzera SPICE model pre SiC MOSFET a na dalsom slajde su typicke krivky
— na slajde je odvolavka na zdrojovu publikaciu (APEC 2017)
— ULOHA pre Tomasa : Zohnat tento clanok („A Physically Based Scalable SPICE Model for Silicon carbide Power MOSFETS, Canhong He, James Victory, APEC 2017, link[2])
— Physical model –> Physically Based SPICE Models

SOURCES:
[1]https://psma.com/sites/default/files/uploads/node/6148/is041-sic-mosfet-corner-and-statistical-spice-model-generation.pdf
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\is041-sic-mosfet-corner-and-statistical-spice-model-generation.pdf
[2] https://www.semanticscholar.org/paper/A-physically-based-scalable-SPICE-model-for-silicon-He-Victory/ee71758e30c727f5ef71dfaa44b11d775ebe449f
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[2] YOU TUBE:  LTspice Modelling of Wolfspeed SiC MOSFET and SiC Diode
— This video demonstrates how to add a SiC MOSFET and SiC diode using Wolfspeed’s (byvaly Cree)SPICE models in a simple DC chopper application.
— LTSpice a  ako pracovat s uz hotovym modelom SiC MOSFET spolocnosti Wolfspeed (https://en.wikipedia.org/wiki/Wolfspeed) a CRES
URL: https://www.youtube.com/watch?v=vFCtCPUcJMg&ab_channel=PowerElectronicswithDr.K
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[3] YOU TUBE: SPICE Compact Models for CoolSiC™ MOSFETs | Infineon
— [1]video v ramci Infinieon Academy
— This training helps you understand how to optimize devices’ behavior in their applications with Infineon’s SPICE Compact Models for CoolSiC™ MOSFETs.
— ULOHY PRE TOMASA:
— vytypovat SiC MOSFET Modul/tranzistor najblizssi pouzitemu v DP (vybrat to podla datasheetu)a vyziadat ho cez stranku [2]
— preskumat na tejto stranke ponuky roznych modelov – medzi nimi su modely SPICE a PSPICE
— stranky Infineon:
— [3]Silicon Carbide MOSFET Modules
— automotive SiC komponenty su uvedene aj tu [4]  CoolSiC™ Products
— stranka venovana modelom Infineon:
— Welcome to Infineon’s Power MOSFET Simulation Models
— [5]doplnujuci material Infineon v PDF : Simulation models for Infineon Power MOSFET Application Note AN 2014-02  V2.0 Feb. 2014
— Infineon ma 4 urovne modelov vykonovycgh suciastok
kap.3 Definition of Modelling Levels
3.1 Infineon Level 0 (basic function)
3.2 Infineon Level 1 (constant temperature)
3.3 Infineon Level 2 (dynamic temperature setting)
3.4 Infineon Level 3 (electro-thermal calculation)
— POZNAMKA: v DP by sme mali urobit aspon Level 0 a preskumat moznost vytvorenia Level 1 az Level 2
— je tam zaujimava veta v kap 6.3 :
„As PSpice was originally not designed for power electronics and highly non-linear components, the standard simulation parameters (Simulation Setup/Options) are often not suitable. In common, the following typicalvalues facilitate convergence: a nasleduje tabulka s parametrami simualcie “
–podobne o nastaveni parametrov simulacie pre komponenty SiC v SPICE sa pise na stranke [6]

SOURCES:
[1]URL: https://www.youtube.com/watch?v=xqPJKhoggOo&ab_channel=Infineon4Engineers
[2]https://www.infineon.com/models
[3] https://www.infineon.com/cms/de/product/power/mosfet/silicon-carbide/modules/?intc=reco
[4] https://www.infineon.com/cms/en/product/technology/silicon-carbide-sic/?redirId=135446
[5]URL: https://www.infineon.com/dgdl/Infineon-ApplicationNote_PowerMOSFET_SimulationModels-AN-v01_00-EN.pdf?fileId=5546d46250cc1fdf0151588db5ef1b18
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\Infineon-ApplicationNote_PowerMOSFET_SimulationModels-AN-v01_00-EN.pdf
[6] http://www.5spice.com/html/sic_models.html
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[4] CLANOK:  Analytical PSpice model for SiC MOSFET based high power modules, 2016
— podrobny popis vytvorenia modelu SiC MOSFET tranzistora
— pracuje sa v SW PSPICE, je tam model a potom aj model kde sa sub model testuje
URL: https://www.sciencedirect.com/science/article/pii/S0026269216300556
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\1-s2.0-S0026269216300556-main.pdf
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[5] Clanok: Study on the Pspice simulation model of SiC MOSFET base on its datasheet, November 2015
–klucovy clanok navod ako vytvorit SPICE model z udajov v datasheete
URL: https://www.researchgate.net/publication/286932470_Study_on_the_Pspice_simulation_model_of_SiC_MOSFET_base_on_its_datasheet
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\290305_FP.pdf
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[6] Clanok: SiC SPICE Model and Analysis for New MOSFETs
— velmi nazorny clanok od Cadence (vyraba OrCAD)- povazujem ho za klucovy pohlad experta na modely SiC MOSFET
— [1] dobry pokec o modeloch – da sa prevziat do kapitoly od modeloch SiC MOSFET
— spomina clanky kde su rozne modely SiC MOSFET tranzistorov
— [2]clanok:   Analytical PSpice model for SiC MOSFET based high power modules tento clanok mame ako [4]
SOURCES:
[1] URL: https://resources.pcb.cadence.com/blog/2020-sic-spice-model-and-analysis-for-new-mosfets
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\SiC SPICE Model and Analysis for New MOSFETs _ Advanced PCB Design Blog _ Cadence.pdf
[2] URL: https://www.mdpi.com/2079-9292/8/5/508/pdf
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\electronics-08-00508.pdf
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[7] Clanok: Sic MOSFET Modeling and Simulation for Pspice, 2015
— dalsi clanok o modeli SiC MOSFET tranzistora
URL: https://www.atlantis-press.com/proceedings/ameii-15/21987
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\21987.pdf
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[8] Clanok: Development of a PSpice Model for SiC MOSFET Power Modules
— [1]clanok si treba kupit
— Abstract:
In this paper, the static and dynamic characteristics of a 1200 V and 120 A silicon carbide (SiC) MOSFET power module has been measured, simulated and verified in the PSpice circuit simulation platform. Experimental measurements and PSpice simulations are performed to extract the technology dependent modeling parameters. The model is implemented in the PSpice circuit simulation platform using both standard components and analog behavior modeling (ABM) blocks. The simulation results of the model is fairly accurate and correlates well with the measured results over a wide temperature range. The developed model is used to facilitate converter design at cell level and hence predict and optimize the cell performance (i.e., energy losses) with varying circuit parameters (e.g., stray inductances, temperatures, gate resistances etc.,).
[1]URL: https://www.scientific.net/MSF.858.1074
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[9] Informativny Clanok: Cree Releases SPICE Model for Silicon Carbide Power MOSFET (2012)
— Cree je firma vyrabajuca SiC MOSFET-y
— [1] clanok informuje o modeloch SPICE a charakterizuje ich ako:
„SiC MOSFETs have significantly different characteristics than silicon devices and therefore require a SiC-specific model for accurate circuit simulations. Cree’s behavior-based, temperature-dependent SPICE model is compatible with the LT spice simulation program and enables power electronics design engineers to reliably simulate the advanced switching performance of Cree CMF10120D and CMF20120D Z-FETs in board-level circuit designs“
SOURCES:
[1]URL: https://eepower.com/new-industry-products/cree-releases-spice-model-for-silicon-carbide-power-mosfet/#
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\Cree Releases SPICE Model for Silicon Carbide Power MOSFET – New Industry Products.pdf
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[10] Clanok: PSpice modeling platform for SiC power MOSFET modules with extensive experimental validation, 2015
— [1] zamknuty IEEE clanok
— abstrakt hovori o simulacii v MATLAB-e a validacii tohoto modelu – pre uvedenie sposobu validacie  je tento clanok dolezity
SOURCES:
[1]URL: https://ieeexplore.ieee.org/document/7855369
LOCAL
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[11] Firemny material ONSEMI (2021 – NOVY!)Physically Based, Scalable SPICE Modeling Methodologies for Modern Power Electronic Devices
— najkompaktnejsi popis zakladneho modelu SiC MOSFET a SiC IGBT vratane popisu verifikacie tohoto modelu
— pre SPICE sa pouziva popis modelu ako „SiC MOSFET Subcircuit Model“
— [1] TOP zdroj pre diploma thesiss vybornou literaturou :
— dalsie materialy ONSEMI :
— [2] tento sa spomina v [16]
— ONSEMI SiC MOSFETs:Gate Drive Optimization
— dolezite pre diploma thesis – vybijanie kondenzatorov sa bude diat v linearnom rezime SiC MOSFET

SOURCES:
[1] URL: https://www.onsemi.com/pub/Collateral/TND6260-D.PDF
LOCAL: c:\Users\pancijra\Downloads\___WORK_DIRS_2022\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\TND6260-D.PDF
[2]URL: https://www.onsemi.com/pub/Collateral/TND6237-D.PDF
LOCAL: c:\Users\pancijra\Downloads\___WORK_DIRS_2022\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\TND6237-D.PDF
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[12] ROHM webstranky o SiC vykonovych polovodicoch – podla [13] jeden z potencialnych dodavatelov SiC komponentov pre SG
— [1] stranka – rozdelovnik „SiC MOSFETs“
— je tam tato charakteristika SiC komponentov :
“ SiC MOSFETs : SiC MOSFETs eliminate tail current during switching, resulting in faster operation, reduced switching loss, and increased stabilization. Lower ON resistance and a compact chip size result in reduced capacitance and gate charge. In addition, SiC exhibits superior material properties, such as minimal ON-resistance increases, and enables greater package miniaturization and energy savings than silicon (Si) devices, in which the ON resistance can more than double with increased temperature. ROHM’s 4th Generation SiC MOSFETOur latest 4th gen SiC MOSFETs provide industry-leading low ON resistance with improving short-circuit withstand time. Additional features include low switching loss and support for 15V gate-source voltage that contributes to further device power savings.“
— dalsie stranky ROHM:
— [2]MOSFET＜Understanding MOSFET Characteristics＞ MOSFET Parasitic Capacitance and Temperature Characteristics:
–popis vlastnosti MOSFET-ov
–[3]Silicon Carbide＜Types of SiC Power Devices＞ SiC SBD Device Structure and Feature
— popis SiC – velmi prehladny , vhodny do Diploma project
–[4]prirucka ROHM v PDF: (nazov) Effective Use of Power Devices Silicon Carbide Power Devices Understanding & Application Examples Utilizingthe Merits
–TOP informacny zdroj
— od slajdu 53 sa venuje vykonovym modulom a ich parametrom a ich pouzitiu
— [5] material ROHM 4th Gen SiC MOSFETs
— DOLEZITA INFORMACIA: graf porovnania Inverter efficiency Mapp IGBT a SiC MOSFET – Significantly improved effciency in the high torque and low rotational speed range
— [6] ROHM ma svoj on-line obvodovy simulator podobny ako je Infineon Designer

SOURCES:
[1] https://www.rohm.com/products/sic-power-devices/sic-mosfet#easyPartFinder
[2] URL: https://www.rohm.com/electronics-basics/transistors/understanding-mosfet-characteristics
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\MOSFET ＜Understanding MOSFET Characteristics＞ _ Electronics Basics _ ROHM.pdf
[3] URL: https://www.rohm.com/electronics-basics/sic/types-of-sic-power
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\Silicon Carbide ＜Types of SiC Power Devices＞ _ Electronics Basics _ ROHM.pdf
[4] URL: https://pages.rohm.com/rs/247-PYD-578/images/TechWeb_E_DL_SiC.pdf
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\TechWeb_E_DL_SiC.pdf
[5] URL: https://www.rohm.com/products/sic-power-devices/sic-mosfet#supportInfo
LOCAL: c:\Users\pancijra\Downloads\___WORK_DIRS_2022\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\SiC MOSFETs – Product Search Results _ ROHM Semiconductor – ROHM Co., Ltd_.pdf
[6] https://www.rohm.com/solution-simulator
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[13] Schaeffler material: Schaeffler Power Electronics Business Division E-Mobility of the Schaeffler Group Business Unit E-Motor & PEU Product Group Power Electronics10/2020
— [1] aktualny status vyvoja PEU v SG vratane uvedenia potencionalnych dodavatelov SIC
— slide str.35: uvedene kto potencialne dodava DIE (nezapuzdrene cipy) (status 2022):
Si IGBTs: – Renesas – ROHM Semiconductor – Infineon – OnSemi (ehm. Fairchild)
SiC MOSFETs: – ROHM Semiconductor – CREE / Wolfspeed- ST Microelectronic
SOURCES:
[1]URL:  https://sconnect.schaeffler.com/docs/DOC-296195
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\PG_Power_Electronics_Unit_Info_Veranstaltung_20201019.pdf
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[14] Schaeffler material (2020): E-Motor & PEU
— stav eMotorov a PEU
— od 35. slajdu popis PEU
SOURCES:
[1]URL: https://sconnect.schaeffler.com/docs/DOC-263745
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\20200128_Schaeffler_eMotoren_PEU_handout.pdf
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[15] Clanok : Temperature Dependent Pspice Model of Silicon Carbide Power MOSFET
— vyzera to tak, ze pouzitelny model SiC MOSFET zohladnuje teplotu –> vid urovne modelov v Infinineon [3]
SOURCES:
[1]URL: https://web.eecs.utk.edu/~tolbert/publications/apec_2012_yutian.pdf
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\apec_2012_yutian.pdf
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[16] TOP INFO Technical Article (2020): How to Simulate Silicon Carbide Transistors with LTspice
— [1] konkretny popis simulacie a  simulacia SiC v LT Spice ma svoje specifika – inak: vsetci simuluju SiC MOSFET v LTSpice – je to referencny nasttroj
— This article reviews the silicon carbide scene and then explains how to get SiC SPICE models and incorporate them into a simulation circuit.
— konkretna simulacia The UCC21750 from Texas Instruments is an example of a gate-drive IC that is compatible with SiC MOSFETsfrom Wolfspeed . This diagram of a three-phase motor-control application is from the device’s datasheet.
— dalsie linky spominane v clanku:
— [2] The Semiconductor of Automotive Power Design: Who’s Offering SiC Components in 2019 (2019) ?
— [3] Exploring the Pros and Cons of Silicon Carbide (SiC) FETs: A New MOSFET from Cree (2017)
— [4]ONSEMI SiC MOSFETs:Gate Drive Optimization
— dolezite pre diploma thesis – vybijanie kondenzatorov sa bude diat v linearnom rezime SiC MOSFET
SOURCES:
[1] URL: https://www.allaboutcircuits.com/technical-articles/how-to-simulate-silicon-carbide-transistors-with-ltspice/
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\How to Simulate Silicon Carbide Transistors with LTspice – Technical Articles.pdf
[2] URL: https://www.allaboutcircuits.com/news/sic-in-2019-whos-offering-sic-components-automotive-power/
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\The Semiconductor of Automotive Power Design_ Who’s Offering SiC Components in 2019_ – News.pdf
[3] URL: https://www.allaboutcircuits.com/technical-articles/pros-cons-silicon-carbide-sic-fets-c3m0075120K-MOSFET-Cree/
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\Exploring the Pros and Cons of Silicon Carbide (SiC) FETs_ A New MOSFET from Cree – Technical Articles.pdf
[4] URL: https://www.onsemi.com/pub/Collateral/TND6237-D.PDF
LOCAL: c:\Users\pancijra\Downloads\___WORK_DIRS_2022\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\TND6237-D.PDF
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[17] technical Articel (2020): tazisko simulqcie v LT Spice  je tu kladene na budenie driverom
— How to Simulate SiC MOSFETs with LTspice: the Importance of a Good Driver
— tazisko simualcie v LT Spice  je tu kladene na budenie driverom
SOURCES:
[1]
URL: https://www.powerelectronicsnews.com/how-to-simulate-sic-mosfets-with-ltspice-the-importance-of-a-good-driver/
LOCAL:
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[18] clanok (2017): modelovanie SiC MOSFET so zapocitanim tepelnych procesov
— Simulation Model of a SiC Power MOSFET Variables Estimation and Control of a Power Source
— modelovanie SiC MOSFET so zapocitanim tepelnych procesov
SOURCES:
[1]
URL: https://www.scitepress.org/papers/2017/64608/64608.pdf
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\64608.pdf
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[19] vedecky clanok  (2021): prostredie MATLAB
— Modeling and analysis of the characteristics of SiC MOSFET
— prostredie MATLAB
SOURCES:
[1]
URL: https://iopscience.iop.org/article/10.1088/1742-6596/2125/1/012051/pdf
LOCAL:…\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\Qiu_2021_J._Phys.__Conf._Ser._2125_012051.pdf
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[20] Clanok IEEE (2017): Analysis of SPICE models for SiC MOSFET power devices
— Analysis of SPICE models for SiC MOSFET power devices
— zamknuty clanok
SOURCES:
[1]
URL: https://www.semanticscholar.org/paper/Analysis-of-SPICE-models-for-SiC-MOSFET-power-Stefanskyi-Starzak/abde07bf3ccc51f67525455f5ff3fe2793f918dc
LOCAL:
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[21] technicky clanok (2020): modelovanie SiC MOSFET v LTSpice, prakticke skusenosti
— Electronic – SiC MOSFET SPICE model not behaving properly
—
SOURCES:
[1]
URL: https://itecnotes.com/electrical/electronic-sic-mosfet-spice-model-not-behaving-properly/
LOCAL:
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[22] Clanok(2022): Specifika modelovania SiC MOSFET
— Improved simulation modelling and its verification for SiC MOSFET
— Specifika modelovania SiC MOSFET
SOURCES:
[1]
URL: https://ietresearch.onlinelibrary.wiley.com/doi/full/10.1049/pel2.12263
LOCAL:…\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\IET Power Electronics – 2022 – Yang – Improved simulation modelling and its verification for SiC MOSFET.pdf
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[23] Clanok (2016): PSpice Modeling Platform for SiC Power MOSFET Modules with Extensive Experimental Validation
— PSpice Modeling Platform for SiC Power MOSFET Modules with Extensive Experimental Validation
SOURCES:
[1]
URL: https://vbn.aau.dk/ws/portalfiles/portal/249465091/EC_0083_PSpice_Modeling_Platform_for_SiC_Power_MOSFET_Modules_with_Extensive_Experimental_Validation.pdf
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\EC_0083_PSpice_Modeling_Platform_for_SiC_Power_MOSFET_Modules_with_Extensive_Experimental_Validation.pdf
[2]
URL: https://www.researchgate.net/publication/310788133_PSpice_Modeling_Platform_for_SiC_Power_MOSFET_Modules_with_Extensive_Experimental_Validation
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\PID4327021.pdf
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[24] Firemny material (2020): MICROCHIPpopis modelov SiC vykonovych komponenetov
— Silicon Carbide Products SPICE & PLECS Files
—
SOURCES:
[1]
URL: https://www.microchip.com/en-us/software-library/sic-products-spice-files
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\SecondGenSpiceFiles.docx
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[25]  Firemny material (2020): WolfSpeed – potencialny dodavatel pre SG
— [1] www stranka „LTspice and PLECS Models“ – su tam aj vsetky SiC MOSFET
— [2] simulator „SpeedFit 2.0 Design Simulator™“
Accelerate the design process with simulation results you can trust. SpeedFit 2.0 quickly calculates losses and estimates junction temperature for power devices based on lab data for common topologies ranging from simple buck and boost converters to a fully bi-directional totem pole PFC with resonant DC/DC converter. Using SpeedFit 2.0, you can quickly determine:
— [3] clanok „Modeling common topologies with Wolfspeed Silicon Carbide MOSFETs“ sa orientuje na LTSpice a modleovanie SiC MOSFEt s cielom dosiahnut/porovnat datsheetove  udaje
— [4] clanok  „Wolfspeed SiC MOSFET SPICE Model Quick Start Guide“ – zaobera sa integraciou modelov SiC MOSFET do programu PSPICE – treba si vsimnut teplotny vstup ktory treba v simulacii  osetrit, ako priklad simualcie s SIC MOSFET-om je uvedeny PSPICE model of the Boost converter (str.9)

SOURCES:
[1] https://www.wolfspeed.com/tools-and-support/power/ltspice-and-plecs-models/
[2] https://www.wolfspeed.com/tools-and-support/power/speedfit/
[3]
URL: https://www.wolfspeed.com/knowledge-center/article/modeling-common-topologies-with-wolfspeed-silicon-carbide-mosfets/
LOCAL: …\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\Modeling common topologies with Wolfspeed Silicon Carbide MOSFETs _ Wolfspeed.pdf
[4]
URL: https://usermanual.wiki/Document/Wolfspeed20SiC20Mosfet20OrCad20Pspice20Model20Quick20Start20Guide2020Rev20102020Feb202018.2143847398.pdf
…\220615 DP VLCEK Tomas\SOURCES\220922 Resers SiC MOSFET SPICE model creation\Wolfspeed20SiC20Mosfet20OrCad20Pspice20Model20Quick20Start20Guide2020Rev20102020Feb202018.2143847398.pdf
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[26] Informacia o simulacnom programe PLECS (2022) spolocnosti PLEXSIM  – program je urceny pre vykonovu elektroniku, ma STANDALONE verziu a verziu ako blockset pre SIMULINK
— [1] stranka na wikipeii
— Wolfspeed na svojich strankach riesi aj integraciu svojich modelov SiC MOSFET tranzistorov do programu PLECS (popri LTSpice a PSPICE)
— [2] uvodne video popisuje STANDALONE verziu
— ULOHA: Zaradit info o tomto programe do diplomovej prace
SOURCES:
[1] https://en.wikipedia.org/wiki/PLECS
[2]  https://www.youtube.com/watch?v=iK2ebV9XcyM&ab_channel=Plexim
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VSEOBECNE

• — semestralka musi byt napisana vo Worde, format taky ako pozaduje AMBIS.CZ (predna strana, obsah, zoznam literatury)
• — odkazy v texte semestralnej prace podla ISO690, prvy prvok a datum -(…. WORD to vie)
• — zoznam literatury (moze byt urobeny automaticky vo WORDE)
• — rozsah –  rozumny – 10-15 stran
• — zasiela sa  doc.Pancikovi na email:
  • na email juraj.pancik(at)ambis.cz
  • predmet emailu: SRI_Prijimeni_Jmeno 
  • v prilohe s nazvom:  SRI_Prijimeni_Jmeno.docx
  • A.  VARIANT SEMESTRALNEJ PRACE 
  • — moze ist o navrh projektu riesenia vybranej ULOHY (vid. portal MBI),
  • — mam pripravit projekt: kto, co (ulohy, podulohy ….), zaco, dokedy ….
  • — zamerat sa na konkretny podnik – v praci nemusi byt menovany
  • — popisat ulohu a vsetky vazby k nej podla oblasti na „kytke“ portalu
  • — nezabudnut na definicie zakladnych pojmov
  • — cele to napisat tak, ze popisem co by som mal/mala robit pri rieseni konkretnej ulohy riadenia IS/ICT pricom  vyuzivam expertnyu pomoc portalu MBI. Cize v seminarnej praci pouzit plural alebo singural, pokojne tam davat pojmy z portalu, URL linky a vsetko tak aby som mohol po case tuto pomoc zrekonstruovat za pomoci portalu MBI.
  • — prihlasit sa a zaregistrovat na portal Vysokej skoly ekonomickej v Prahe https://mbi.vse.cz/mbi/index.html
  • — vybrat si svojmu srdcu blizku ulohu riadenia v informatike, ktora ma odraz v praci studenta
  • B.  VARIANT  SEMESTRALNEJ PRACE 
  • — moze ist o profilovu semestralnu pracu z portalu MBI so zameranim na studentom vybrany pojem napr. ROLA, MODEL, INFRASTRUKKTURA, PERSONAL. V takto koncipovanej praci sa predstavia jednotlive aspekty domeny (ULOHY, SCENARE, FAKTORY….) tak ako su na lavej strane
  • cerpat z portalu a vsade davat odkazy – prosto povedat toto som sa docital na portali MBI tam a tam a da sa v tom pokracovat
  • C.  VARIANT  SEMESTRALNEJ PRACE   <— …. ODPORUCAM vzhladom na situaciu kedy nam chyba kontaktna vyucba …..
  • — popis Vam znameho informacneho systemu , popisat prezentacnu, aplikacnu a databazovu cast informacneho systemu, t.j. pouzivatelske rozhranie, popis ktore procesy informacny system podchytava a pokusit sa popisat strukturu udajov a manipulaciu s nimi v databaze informacneo systemu
• — priklady semestralnych prac  vid LINK a u mna doma v adresari …\200318 AMBIS StudWork Management IS a ICT\200318 AMBIS StudWork Management IS a ICT.zip
• — ked to urobite takto tak to bude fajn ….

POKYNY: 

1. Stiahnite si knihy [1][2] z Google Disc z linku uvedeneho dole
2. Najdite svoje meno v TABULKE dole   a dve Vam pridelene teoreticke otazky
3. Rukou napiste na papiere formatu A4  otazky a odpovede  na Vam  pridelene  teoreticke otazky
4. Zoskenujte vypracovane odpovede do formatu PDF a poslite mi subor na email adresu juraj.pancik@feit.uniza.sk s predmetom emailu: RSICE_PRIEZVISKO_MENO
5. Termin zaslania je koniec Vasho skuskoveho obdobia – t.j. koniec maja 2020.
6. Ide o nahradu Vasej ustnej skusky z RSICE  – v danej situacii (pandemia COVID-19 a dokoncievanie Vasich Bc prac) to vidim ako rozumne riesenie – velmi to vsak dalej nesirte

Zdroje:  stiahnutelne z linku https://drive.google.com/open?id=1pQHowwd7akn3PEaJvK911QOC92lb93KH

[1] TOP AUTOMOTIVE Understanding Automotive Electronics Eighth Ed. An Engineering Perspective.pdf
[2] BOSCH Diesel  engine management systems 3658039809.pdf

TABULKA: 

• Toto je scenar cvicenia SEM5  z predmetu Mikroprocesorove systemy Leto 2020 pondelok 20.4. a utorok 21.4. 2020  

• Studenti vykonaju kroky podla scenara doma – vyucba je prerusena koli epidemii korona virusu

• Stiahnite  potrebne subory  LINK       

*****************************************************
TEMA [A] Priprava – prerekvizity
ULOHA: Do adresara c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\ s prikladmi pridat podadresar s dalsimi prikladmi
POSTUP:
1. nahrat ZIP subor [1] z www.drpancik.sk. ZIP obsahuje zdrojove subory
2. rozpakovat tento subor do adresara [2]

[1] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200313 MSP430 STUDY Examples of driverlib for the TI MSP430F5529 LaunchPad\MSP430F5529_driverlib_examples-master.zip
alebo
DOWNLOAD z DRPANCIK website vid. LINK  

[2] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\MSP430F5529_driverlib_examples\
*****************************************************

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TEMA [B] Priprava vychodiskoveho projektu – uz je nam znamy
ULOHA: blikanie cervenou ledkou po 1s, programovanie s vyuzitim kniznice MSP430Ware: driverlib.h
POSTUP:
1. Naimport projekt do workspace : lab_03a_gpio_solution_msp430f5530 [1]
2. Preklad a debagovanie tohoto projektu
CO VIDIET: raz za sekundu zablikne cervena LED-ka

[1] IMPORT Z : c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\msp_workshop\lab_03a_gpio_solution_msp430f5529\
*****************************************************

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TEMA [C] Priprava vychodiskoveho projektu – tento nam este nie je znamy
ULOHA: Vysielanie znakov na konzolu , programovanie s vyuzitim kniznice MSP430Ware: driverlib.h
POSTUP:
1. Skopirujem si projekt lab_03a_gpio_solution_msp430f5530 vo workspace a vlozim si ho znova do workspace s menom 04A_console_printf
2. Zamenim si subor lab_03a_gpio_solution_msp430f5530 suborom 04A_console_printf.c [1]
3. Preklad a debagovanie tohoto projektu POZNAMKA: pre opakovanie ladenia pouzite Run –> Restart
CO VIDIET: 10 x sa vysle na seriovu linku hlasenie „Hello World x (x od 1 do 10)“
DOLEZITE POZNAMKY:
— vsimnut si ze do zdrojoveho kodu pribudla driverlib.h okrem hlavicka #include <stdio.h> // to include printf()
— nastavit si podla textu v zdrojaku [1] „Right click project –> Properties –> MSP430 Linker –> Basic Options* Increase the Heap size to 320“ to use printf()

[1] ZDROJOVY SUBOR: c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\MSP430F5529_driverlib_examples\04A_console_printf (ide o vysielanie na seriovu linku, na konzolu)
#TASK: vytvorim si projekt 04A_console_printf`s a driverlib.h a tymto vzorovym suborom 04A_console_printf –> debagujem a sledujem seriovu linku

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TEMA [D] „Zmergovanie“ Spojenie dvoch projektov
ULOHA: pri kazdom zabliknuti cervenej LED sa 10x vyse na seriovu linku „Hello world“
POSTUP:
1. Premenujem si projekt lab_03a_gpio_solution_msp430f5530 na lab_03a_gpio_solution_hello_world_msp430f5529 (kniznica driverlib.h zostane aktivna )
2. Spojim kod do kodu lab_03a_gpio_solution_msp430f5530.c vlozim cast kodu zo suboru 04A_console_printf.c
3. Prelozim a debagujem program
CO VIDIET: Po kazdom zabliknuti cervenej LEDKY sa 10 x sa vysle na seriovu linku hlasenie „Hello World x (x od 1 do 10)“
MOZNE SPRAVNE RIESENIE: [1]

[1] c:\STUDENT\FILES for distance MS students\lab_03a_gpio_solution_hello_world_msp430f5529\main.c
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DOMACA ULOHA:
0. — tieto priklady budu na skuske
— do zosita #MyCodeDiary si zapiste vsetko podstatne na skuske tento zosit mozete mat

1. Zmodifikovat projekt lab_03b_button_solution_msp430f5529 [1] tak, ze po kazdom stlaceni tlacitka S2 sa 10 x sa vysle na seriovu linku hlasenie „Hello World x (x od 1 do 10)
Projekt premenovat vo workspace na lab_03a_button_solution_hello_world_msp430f5529.
POZNAMKY:
— pred prekladom (buildom) citat DOLEZITE POZNAMKY v TEMA [C]
— pri debagovani pokojne pouzit Run –> Restart , program sa vzdy vrati do vychodiskoveho stavu
— sledujte co sa deje v console okne

2. Zmodifikovat projekt lab_03b_button_solution_msp430f5529 [1] tak, ze po stlaceni tlacitka S2 sa rozsvieti cervena LED a na konzolu vypise „Svieti CERVENA LED“ a po stlaceni tlacitka S1 sa rozsvieti zelena LED a na konzolu sa vypise „Svieti zelena LED“.
Projekt premenovat vo workspace na lab_03a_button_solution_RED_GREEN_LED_msp430f5529.

Prosim, poslat obidva .c zdrojove subory (vynat ich z projektov) a poslat ich na juraj.pancik(at)feit.uniza.sk s predmetom emailu MS_PRIEZVISKO_MENO a v ZIP-e(RAR-e) s nazvom MS_PRIEZVISKO_MENO.ZIP (RAR)
[1] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\msp_workshop\lab_03b_button_solution_msp430f5529\
*****************************************************

*****************************************************

• Toto je scenar cvicenia SEM4  z predmetu Mikroprocesorove systemy Leto 2020 pondelok 9.3. (skupina A, cvicenie bolo ) a utorok 10.3. 2020 (skupina B, toto cvicenie nebolo)  

• Studenti skupiny B vykonaju kroky podla scenara doma – vyucba je porerusena koli epidemii korona virusu  

• Domaca uloha :  
  • 1. nainstalovat si Code Composer Studio a MSP430 Ware
  • 2. doma s CSS ver.9 si urobit priklady    3.kap. MSP430 Workshop (lab_03a_button_solution_msp430f5529 , lab_03b_gpio_solution_msp430f5529)
  • 3. nakreslit vyvojovy diagram (flowchart) Vasej konzolovej aplikacie v C-ku do pracovneho zosita – o portovani na platformu MSP430 este budeme hovorit  
• Scenar cviceni SEM 4 : 
  • — informovanie sa – kontrola domacej ulohy – vsetkym funguju ich kity ? Vedeli studenti urobit projekty v CCS ver.9. dma ?
  • — debagovanie programov v kapitole 3. –> breakpoint v programe lab_03a_button_solution_msp430f5529 ,  zmeny registrov, zapis otazok do FAQ a preskusavanie studentov,  vytvorenie rozsirenia tychto dvoch programov o vysielanie sprav na seriovu linku
  • — prejst si datasheet [1] a users guide [2] k MSP430F5529  #AdFAQ (pridat otazku do do FAQ)
  • — prejst si library drivelib users guide [3] vo vztahu k prikladom
  • — ukazat / prehladat  adresny priestor MSP430 v DEBUGGERI vratane umiestnenia registrov pre GPIO porty. Vedia studenti dohladat adresy tychto portov ? TRENOVAT TENTO PROBLEM.  Doplnit do FAQ: ukazte adresny priestor v DEBUGGERI pre Port1 , pre vektor prerusovacich rutin, ……
  • — dopisat otazky a odpovede na prakticku skusku do FAQ listu
  • — diskutovat s kazdym studentom moznosti portovania jeho programu v C do MSP430
  • — AGENDA:
    • — tim GHURA-MURIN : rozchodili CSS ver.9 doma ?
    • — informovat o pisomke v SEM5 z UML – spomenut zdroje kt. su k dispozicii – vid. zapis PRED 3
• Refres informacii: casto kladene otazky z cvicenia #FAQ a #TODO list vid. LINK  – obe posluzia ako namety na  skusku
• ZDROJE:
• [1] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430F552x, MSP430F551x DataSheet.pdf
• [2] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430x5xx and MSP430x6xx Family User’s Guide.pdf
• [3] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430F5xx_6xx_DriverLib_Users_Guide-2_91_12_08.pdf

ZAPIS Z PREDNASKY :
— prva prednaska
— oboznamenie s podmienkami ukoncenia predmetu a s hodnotenim
— hovorime o troch varianatch semestralnej prace –> studenti sa priklanaju k variantu C. – popis informacneho systemu vo svojom okoli (vid. variant C [1]) – tento informacny system vyucivaju ako pouzivatelia
— hovorime im co by mali vidiet pod pojmami: prezentacna, aplikacna a databazovu cast popisovaneho informacneho systemu – budeme sa k tomuto este vracat na konkrertnych prikladoch
— vysvetlujeme si postup analyzy informacneho systemu tak ako ho popisala analyticka obchodnych procesov (busines analytik na profesia.sk) Ing. Danica Polakova vo svojej bakalarskej praci , vid. PRILOHA 2 v [1]
— Danica urobila analyzu informacneho systemu elektronickej podatelne :
— — vysla zo zakonnych poziadaviek na takyto informacny system,
— — urobila procesny model existujuceho stavu v jazyku BPMN (vid heslo na ceskej Wikipedii BPMN [3]),
— — nasledne spisala vsetky funkcne a nefunkcne poziadavky,
— — navrhla optimalizovany procesny model elektronickej podatelne v jazyku BPMN,
— — vytvorila model – diagram v jazyku UML pripadov pouzitia a
— — nasledne podrobne scenare pripadov pouzitia
— na zaklade tohoto vieme odvodit prezentacnu, aplikacnu a databazovu vrstvu informacneho systemu – to budeme pokracovat nabuduce
— z prednasky na slajdoch hovorime o pojmoch ako informatika, informacia, data, informacni system, system, staticky a dynamicky popis systemu; hovorime o osobnostiach informatiky ako Allan Turing [5] a jeho tragickom osude genia, o John von Neuman [6] a o Claude Shannon [7] a jeho genialna diplomova praca
— v zavere prednasky sa venujeme organizacii informacii na portali MBI VSE Praha [8] a o vazbe riadenia podniku a riadenia IT v podniku podla portalu [8] i podla odporucanej literaury [9]
PLAN NABUDUCE:
— 1. Ako odvodit prezentacnu, aplikacnu a databazovu vrstvu informacneho systemu na zakalde jeho pozorovania a jeho pouzivania, opakovanie principu architektury IS KLIENT-SERVER (tenky a hruby klient)
— 2. Pokracovanie: vazbe riadenia podniku a riadenia IT v podniku
— 3. Strategicke riadenie podniku a strategicke riadenie IT v podniku podla portalu MBI [8]
— 4. Faktory IT: aplikace IT [10]

ZDROJE:
[1]– Závěrečná bc práce: Danica Poláková: „Správa a modelovanie požiadaviek zákazníka“r.2011
— URL: https://is.ambis.cz/th/14379/bisk_b/?lang=sk
— na nu nadvazuje jej diplomova praca „Postupy analýzy informačného systému s využitím UML“ r.2013
URL: https://is.ambis.cz/th/mfigl/
[2] http://www.drpancik.sk/management-is-ict-leto-2020-popis-semestralnej-prace/
[3] https://cs.wikipedia.org/wiki/Business_Process_Model_and_Notation
[4] https://cs.wikipedia.org/wiki/Unified_Modeling_Language
[5] https://en.wikipedia.org/wiki/Alan_Turing
[6] https://en.wikipedia.org/wiki/John_von_Neumann
[7] https://en.wikipedia.org/wiki/Claude_Shannon
[8] https://mbi.vse.cz/
[9] Gála Libor, Šedivá Zuzana, Pour Jan: Podniková informatika
Počítačové aplikace v podnikové a mezipodnikové praxi – 3., aktualizované vydání
Datum vydání: 18. 09. 2015
ISBN: 978-80-247-5457-4
E-kniha ePUB, PDF, Kindle 203 Kč
https://www.grada.cz/podnikova-informatika-(1)-8588/
[10] USB kluc …\_Management_IS_ICT\STUDY\200215 STUDY Management IS_ICT Portal MBI VSE Praha\Faktory IT aplikací FG300_cs.pdf

• MS_A_skupina_SEM.1. pondelok 17.2.2020 
• — delenie skupin na cvicenia (L, laboratoria) : st. skupina 3Z2C20 autotronika ma v utorky – 12 studentov – v pondelky maju predmet ECV , ostatni studenti pridu v pondelok
• — studenti poslali doc. P. kontaktne e-maily
• — kopirujeme obsah sprievodneho USB kluca do adresara [4]
• — instalujeme PC vyvojove prostredie pre Code::Block [1] a MSP430WAre [2]
• — testujeme ci nam Code::Block prelozi projekt ATM terminal v C++[3]  – ide to
• — presli sme si zakladne informacie ku TI Launchpadu MSP430F5529 [4][5]
• –#TASK: v [5] popisany demo example (emulacia USB externa pamat) je perfektne demo co dokaze tento procesor – studovat podrobnejsie
• –#TASK: popisat podrobnejsie BOOSTER SENSOR – napr. PC program pre riadenie a vizualizaciu senzorov
• — diskusia k prieskumu StackOverflow [7] – hovorime o rozdieloch v kodoch z C++ a C# a JAVA, o behovych prostrediach JVM a .NET, o popularnych jazykoch JavaScript/HTML/CSS (behove prostredie je webovy prehliadac) , o programovani serverov pomocou JavaScript (projekt node.js)
• [1] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\INSTALL\INSTALL CODE BLOCK and MINGW C C++ COMPILER ver.17.12\
• [2] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\INSTALL\INSTALL MSP430Ware_3_80_08_01\
• [3] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200126 STUDY DEITEL ATM terminal in C++\
• [4] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\
• [5] c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430F5529 LaunchPad Development Kit slau533d.pdf
• [6]c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430F5529 USB LaunchPad Evaluation Kit slau536.pdf
• [7] https://insights.stackoverflow.com/survey/2019#overview
• — POZNAMKA: uloha #MyAlgorithmWorkshop moze byt aj ina samostatna prac po dohode so studentom za 40% a viac
• — DOMACE ULOHY NA BUDUCE CVICENIE : 
• — — 1.  kupit si zosit #MyCodeDiary – A4 format
• — — 2. nainstalovat si Code Composer Studio a MSP430 Ware
• — — 3.  poslat email MS_PRIEZVISKO_MENO
• — DOMACE ULOHA PRE doc. P. NA BUDUCE CVICENIE : 
• — 1. objedna kity MSP_430  [1] pre 3 studentov , Mario ma, Frantisek chce dva:  t.j. 4ks
• [1] https://sk.farnell.com/texas-instruments/msp-exp430f5529lp/usb-launchpad-evaluation-kit/dp/2357895?st=TI%20launchapd%20MSP430F5529
• MS_B_skupina_SEM.1. utorok 18.2.2020 
• — presli sme to co so  skupinou A – vid. LINK
• — DOMACE ULOHY NA BUDUCE CVICENIE : 
• — — 1.  kupit si zosit #MyCodeDiary – A4 format
• — — 2. nainstalovat si Code Composer Studio a MSP430 Ware
• — — 3.  poslat email MS_PRIEZVISKO_MENO

• 0. AGENDA: dochadzka,  zaslane domace ulohy, rozdelenie kitov  MSP430
• 1. Zopakovat si pojmy a prejst si kap.1 a kap.2 z MSP430 Design workshop [1]
• 2. Prejst si priklad z konca hodiny SEM2 CVICENIE – preblikavanie s LED-kami  – vysvetlit ako funguje – dohladat v USERS GUIDE  [2] a DATASHEET [3] nazvy registrov
• 3. Prejst si kap.3
• 4. Venovat sa niektorym prikladom #MyLastProject_in_C zaslanym na portaciu:
  • — nakreslenie  algoritmu ACTIVITY DIAGRAM do  #MyAlgorithmWorkshop
  • — spustenie programu na PC v IDE #CodeBlock
  • — pokus o portaciu na MPS430 v IDE CCS
• 5. Doplnenie otazok a prikladov do #SurvivalList
• ZDROJE: 
• [1] d:\__VYUCBA_UNIZA\LETO_2020\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP_Design_Workshop.pdf
• [2] d:\__VYUCBA_UNIZA\LETO_2020\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430x5xx and MSP430x6xx Family User’s Guide.pdf
• [3] d:\__VYUCBA_UNIZA\LETO_2020\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430F552x, MSP430F551x DataSheet.pdf

• Prolog:
• — — Student si urobia Upgrade obsahu USB kluca.
• — — Este raz overime pocet potrebnych kitov TI LAUNCHAPD  na objednanie.
• TEMA: Import projektov 
• 0. Otvorit si manual ON-LINE k TI CSS :  https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_glossary.html
• 00. Zakladny dokument podla ktoreho pojdeme vo vyucbe : c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP_Design_Workshop.pdf
• 000. Manual k nami pouzivanym procesorom MSP430 : c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\STUDY\200212 STUDY MSP430 from Texas Instruments\MSP430x5xx and MSP430x6xx Family User’s Guide.pdf

• 1. Obnova rozlozenia okien v CCS (TI Code Composer Studio):
• — Windows –> Perpective –> Reset Perspective
• — Windows –> Perpective –> Open Perspective –> CCS edit (default)
• 2. Priprava CSS na pracu :
  • — s podadresarom sa  c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020  sa „nehybe“   bude sluzit aj pri skuske ako zdroj informacii 
  • — kazdy student ma svoj podadresar  C:\STUDNET  – tam sa kopiruju vychodzie projekty
  • — vymazanie (DELETE) vsetkych projektov v Project Explorer
  • — vytvorenie si podadresara s PRIEZVISKOM vo workspace – tam si da student svoje projekty vytvorene v CSS
  • — do workspace sa nic nekopiruje je to TOXICKE . mozu sa tam robit len poddresare s nazvom PRIEZVISKO studenta 
• 3. Priprava suborov pre pracu :
• — kopirovanie z c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\msp_workshop\lab_02a_ccs_solution\ do c:\STUDENT\Youth_PANCIK\lab_02a_ccs_solution\
• — c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\msp_workshop\lab_02b_blink_solution\ do c:\STUDENT\Youth_PANCIK\lab_02b_blink_solution\
• — c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\Mikroprocesorove systemy – cvicenia\Cv1_1_GPIO\ do c:\STUDENT\Youth_PANCIK\Cv1_1_GPIO\
• — c:\STUDENT\Mikroprocesorove_Systemy_LETO_2020\WORK\Mikroprocesorove systemy – cvicenia\Cv2_1_GPIO\ do c:\STUDENT\Youth_PANCIK\Cv2_1_GPIO\
• 4. Import vsetkych styroch projektov do workspace CSS a nasledne CLEAN –> BUILD –> DEBUG
• 5. Podrobne vysvetlenie vsetkych programov, krokovanie a prezerane premennych
• 6. Vytvorenie otazok pre skusku tak, ze vsetky informacie su na pocitaci
• TEMA: vytvorenie noveho projektu so pripravenym zdrojovym suborom main.c
• — vytvorit novy projekt pre MSP430F5529 bez main().c
• — pridat subor main.c  Vid.:  c:\STUDENT\PANCIK\Cv2_1_GPIO\main.c – preblikavanie LED-iek (CERVENA LED P1.1 a ZELENA LED P4.7)
• — krokovat projekt
• — modifikovat subor o opakovanie preblikavania LED:

• main.c
  #define WDGCTL (*((unsigned int *) 0x015C))
  #define PORT1DIR (*((unsigned int *) 0x0204))
  #define PORT4DIR (*((unsigned int *) 0x0225))
  #define PORT1OUT (*((unsigned int *) 0x0202))
  #define PORT4OUT (*((unsigned int *) 0x0223))
  
  
  #define BIT0 0x01
  #define BIT1 0x02
  #define BIT2 0x04
  #define BIT3 0x08
  #define BIT4 0x10
  #define BIT5 0x20
  #define BIT6 0x40
  #define BIT7 0x80
  
  void dellay() {
  volatile unsigned int i; // volatile to prevent optimization
  i = 10000; // SW Delay
  do i--;
  while(i != 0);
  }
  
  /*
  * main.c
  */
  int main(void) {
  volatile unsigned char ucPrem;
  volatile signed char scPrem;
  volatile unsigned int uiPrem;
  volatile int iPrem;
  
  WDGCTL = 0x5A00 | 0x80; // Stop watchdog timer
  
  ucPrem = 0b11111111;
  scPrem = 127;
  ucPrem++;
  scPrem++;
  
  uiPrem = 0xFFFF;
  iPrem = -32768;
  uiPrem++;
  iPrem--;
  
  //asm(" BIS.W #1,&0x0204");
  PORT1DIR |= BIT0;
  PORT4DIR |= (unsigned int)(BIT7<<8);
  
  PORT1OUT |= BIT0;
  PORT4OUT |= (unsigned int)(BIT7<<8);
  
  PORT1OUT &= ~BIT0;
  PORT4OUT &= ~((unsigned int)(BIT7<<8));
  
  PORT1OUT |= BIT0;
  PORT4OUT |= (unsigned int)(BIT7<<8);
  
  while(1) {
  volatile unsigned int i; // volatile to prevent optimization
  
  PORT1OUT |= BIT0;
  dellay();
  PORT4OUT |= (unsigned int)(BIT7<<8);
  dellay();
  PORT1OUT &= ~BIT0;
  dellay();
  PORT4OUT &= ~((unsigned int)(BIT7<<8));
  dellay();
  }
  // return 0;
  }

Clanok bol transformovany na stranku LINK